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unisonic technologies co., ltd 8565 preliminary linear integrated circuit www.unisonic.com.tw 1 of 13 copyright ? 2012 unisonic technologies co., ltd qw-r114-004.b high performance power factor correction controller in continuous conduction mode ? description the utc 8565 is a wide input range controller integrated circuit for active power factor correction. the circuit is designed for boost pfc application, and requires reduced external component count. its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the ic. the circuit operates in the contin uous conduction mode under average current, and in discontinuous conduction mode only in light load condition. the switching frequency can be set with the external resistor at pin 4. both current and voltage loop compensations are done externally to allow full user control. there are many kinds of protection featur es incorporated to make sure of safe system operation conditions, such as brown-out protection, output under volt age detection and peak current limitati on. the inside reference is adjusted (5v2%) to make sure control level and precise protection. there is a particular soft-start function to limit the start up current and thus reduces t he stress on the boost diode. ? features * supports wide input range * average current control * ease of use with few external components * external current and voltage loop compensation * trimmed internal reference voltage (5v2%) * programmable operating/switching frequency * (50khz ~ 250khz) * max duty cycle of 95% (typ) at 125khz * under voltage lockout * cycle by cycle peak current limiting * over-voltage protection * open loop detection * output under-voltage detection * brown-out protection * soft over current protection * enhanced dynamic response ? ordering information ordering number package packing lead free halogen free 8565l-s08-r 8565g-s08-r sop-8 tape reel 8565l-s08-t 8565G-S08-T sop-8 tube (1) r: tape reel, t: tube (2) s08: sop-8 (3) g: halogen free, l: lead free 8565l-s08-r (1)packing type (2)package type (3)lead free
8565 preliminary linear integrated circuit unisonic technologies co., ltd 2 of 13 www.unisonic.com.tw qw-r114-004.b ? pin configuration 1 2 3 4 5 6 7 8 i sense i comp gnd freq v cc gate v sense v comp ? pin description pin no. pin name description 1 v sense the output bus voltage of the boost converter is sensed at th is pin via a resistive divider. the reference voltage for this pin is 5v. 2 v comp this vcomp pin provides the compensati on of the output voltage loop with a compensation network to ground (see fig. 2). this also gives the soft start function which controls an increasing ac input current during start-up. 3 i comp at this pin the compensation components of the current loop are connected. the capacitor which is connected at this pin integrates the output current of ota2 and averages the current sense signal. 4 freq a resistor connected to this pin sets the fi xed switching frequency. the frequency range is from 50khz to 250khz. 5 i sense the pin senses the negative voltag e drop at the external sense resistor (r1). this is the input signal for the average current regulation in the current loop. it is also fed to the peak current limitation block. during power up time, high inrush currents cause high voltage drop at r1, driving currents into pin 5 which could be beyond the absolute maximum ratings. therefore a series resistor (r2) of around 220 ? is recommended in order to limit this current into the ic. 6 gnd this is the ground pin. 7 gate the gate pin is the output of the internal driver stage, whic h has a capability of 1.5a source and sink current. its gate drive voltage is clamped at 11.5v (typically). 8 v cc the v cc pin is the positive suppl y of the ic and should be connected to an external auxiliary supply. the operating range is between 10v and 21v. the turn-on threshold is at 11.2v and under voltage occurs at 10.2v.
8565 preliminary linear integrated circuit unisonic technologies co., ltd 3 of 13 www.unisonic.com.tw qw-r114-004.b ? block diagram c2 d1 vin 85...265 vac rfi filter d2...d5 c1 l1 r1 r7 r4 r3 v out r2 gnd utc 8565 freq r5 variable oscillator 2.5v ota3 + - osc clk 250ns toff min peak current limit over-current comp 300ns 1.5v c2 + - deglitcher i sense op1 current sense opamp -1.43x current loop i comp current loop comp ota2 1.1ms +/-50 a linear range s2 c3 fault 4.0v nonlinear gain + - c1 ramp generator pwm comp r s r s pwm logic v cc auxiliary supply gate gate driver protection block v cc uv lockout + - c4 2.5v oup + - c3 0.8v olp v sense v comp r6 c4 c5 s1 fault 4.0v soft start +/-30 a, 42 s 5v ota1 + - voltage loop 0.73v 0 -ve soft over current control 4.75v 5.25v +ve 0 -ve window detect protection logic + - fault representative block diagram
8565 preliminary linear integrated circuit unisonic technologies co., ltd 4 of 13 www.unisonic.com.tw qw-r114-004.b ? absolute maximum ratings parameter symbol ratings unit v cc supply voltage v cc -0.3 ~ 22 v freq voltage v freq -0.3 ~ 7 v icomp voltage v icomp -0.3 ~ 7 v isense voltage v isense -24 ~ 7 v isense current i isense 1 ma vsense voltage v vsense -0.3 ~ 7 v vsense current i vsense 1 ma vcomp voltage v vcomp -0.3 ~ 7 v gate voltage v gate -0.3 ~ 22 v esd protection (note 2) v esd 2 kv junction temperature t j -40 ~ 150 c storage temperature t stg -55 ~ 150 c notes: 1. absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. 2. according to eia/jesd22-a114-b (discharging a 100pf capacitor through a 1.5k ? series resistor) ? thermal data parameter symbol ratings unit junction to ambient ja 90 k/w ? electrical characteristics parameter symbol test conditions min typ max unit operating range (note 1) v cc supply voltage v cc v ccuvlo 21 v junction temperature t j ( con ) -40 125 c supply section (note 2) v cc turn-on threshold v ccon 10.5 11.2 11.9 v v cc turn-off threshold/ under voltage lock out v ccuvlo 9.4 10.2 10.8 v v cc turn-on/off hysteresis v cchy 0.8 1 1.3 v start up current before v ccon i ccstart v vcc =v vcc ( on ) -0.1v 50 100 200 a operating current with active gate i cchg r5=33k ? , c l =4.7nf 13.5 18 22.5 ma operating current during standby i ccstdby r5 = 33k ? , v vsense =0.5v 2.0 2.6 3.2 ma variable frequency section switching frequency (typical) f swnom r5=33k ? 106 133 161 khz switching frequency (min.) f sw ( min ) r5=82k ? 40 56 70 khz switching frequency (max.) f sw ( ma x ) r5=15k ? 200 250 320 khz voltage at freq pin v freq 2.40 2.50 2.60 v pwm section max. duty cycle d max f sw =f swnom (r5=33k ? ) 92 95 98 % min. duty cycle d min v vcomp =0v, v vsense =5v, v icomp =6.4v 0 % min. off time t off ( min ) v vcomp =5v, v vsense =5v, v isense =0.1v 150 250 350 ns
8565 preliminary linear integrated circuit unisonic technologies co., ltd 5 of 13 www.unisonic.com.tw qw-r114-004.b ? electrical characteristics(cont.) parameter symbol test conditions min typ max unit system protection section open loop protection (olp) v sense threshold v olp 0.77 0.81 0.86 v peak current limitation (pcl) i sense threshold v pcl -1.15 -1.08 -1.00 v soft over current control (soc) i sense threshold v soc -0.79 -0.73 -0.66 v output under voltage detection (ouv) v sense threshold v ouv 2.45 2.55 2.65 v output over-voltage protection (ovp) v ovp 5.12 5.25 5.38 v current loop section ota2 transconductance gain gm ota2 at temp=25c 0.9 1.1 1.3 ms ota2 output linear range i ota2 guaranteed by design 50 a i comp voltage during olp v icompf v vsense =0.5v 3.6 4.0 v voltage loop section ota1 reference voltage v ota1 4.90 5.00 5.10 v ota1 transconductance gain gm ota1 31.5 42 52.5 s ota1 max. source current under normal operation i ota1so v vsense =4.25v, v vcomp =4v 21 30 38 a ota1 max. sink current under normal operation i ota1sk v vsense =6v, v vcomp =4v 21 30 38 a soft start end v soft 3.80 4.00 4.20 v ota1 source current under soft start i ota1ss v vsense =2v, v vcomp =0v 8.0 10.8 13.4 a enhanced dynamic response v sense high v hi 5.12 5.25 5.38 v v sense low v lo 4.63 4.75 4.87 v v sense input bias current at 5v i vsen5v v vsense =5v 0 1.5 a v sense input bias current at 1v i vsen1v v vsense =1v 0 1 a v comp voltage during olp v vcompf v vsense = 0.5v, i vcomp =0.5ma 0 0.2 0.4 v driver section gate low voltage v gatel v cc =5v, i gate =5ma 1.2 v v cc =5v, i gate =20ma 1.5 v i gate =0a 0.8 v i gate =20ma 1.6 2.0 v i gate =-20ma -0.2 0.2 v gate high voltage v gateh v cc =20v, c l =4.7nf 11.5 v v cc =11v, c l =4.7nf 10.5 v v cc =v vcc ( off ) +0.2v, c l =4.7nf 7.5 v gate rise time t r v gate =2v...9v, c l =4.7nf 20 ns gate fall time t f v gate =9v...2v, c l =4.7nf 20 ns gate current, peak, rising edge i gate c l =4.7nf (note 3) -1.5 a gate current, peak, falling edge i gate c l =4.7nf (note 3) 1.5 a notes: 1. within the operating range the ic operat es as described in the functional description. 2. the electrical characteristics in volve the spread of values within the specified supply voltage and junction temperature range t j from -40c to 125c. typical values repr esent the median values, which are related to 25c. if not otherwise st ated, a supply voltage of v cc =15v is assumed for test condition. 3. design characteristics (not meant for production testing)
8565 preliminary linear integrated circuit unisonic technologies co., ltd 6 of 13 www.unisonic.com.tw qw-r114-004.b ? functional description 1. general the utc 8565 is an active power factor correction controlle r for boost pfc application. the ic comes in dip package and is suitable for wide input range applications from 85 to 265 v ac . the ic is usually realized with boost converters and it operates in continuous co nduction mode with average current control. the utc 8565 operates with a cascaded control; the inner current loop and t he outer voltage loop. the inner current loop of the ic cont rols the sinusoidal profile for the average input current. it uses the dependency of the pwm duty cycle on the line input voltage to determine th e corresponding input current. this means the average input current follows the input voltage as long as the device operates in cc m. under light load condition, depending on the choke inductance, the system may enter into di scontinuous conduction mode (dcm). in dcm, the average current waveform will be distorted but the resultant harmonics are still low enough to meet the class d requirement of iec 1000-3-2. the outer l oop controls the output voltage. depending on the load condition, ota1 establishes an appropriate voltage at v comp pin which controls the amplitu de of the average input current. the utc 8565 provides several protection feat ures to ensure safe operating co ndition for both the system and device. important protection features are namely brown-out protection, current limitation and output under-voltage protection. 2. power supply the operating voltage range of the v cc is from 10v to 21v. an internal under voltage lockout (uvlo) block monitors the v cc power supply. as soon as it exceeds 11.2v and the voltage at pin 1 (v sense ) is >0.8v, the ic begins operating its gate drive and performs its soft-start as shown in fig. 3. if v cc drops below 10.2v, the ic is off. the ic will t hen be consuming typically 200a, whereas consuming 18ma during normal operation. the ic can be turned off and forced into standby mode by pulling down the voltage at pin 1 (v sense ) to lower than 0.8v. the current consumption is reduced to 3ma in this mode.
8565 preliminary linear integrated circuit unisonic technologies co., ltd 7 of 13 www.unisonic.com.tw qw-r114-004.b ? functional description(cont.) 3. start-up (soft-start) the operation of ota1 during start up is shown in fig. 4 and 5. v sense ( ) r4 r3+r4 v out 10.8 a during soft start v comp r6 c4 c5 utc 8565 0.8v c3 - + s1 5v - + ota1 soft start 4.0v fig. 4 soft start circuit soft start normal operation v out <80% rated v out >80% rated t av(i in ) fig. 5 soft start with controlled current open-loop protect (olp) it sources a constant 10.8a into the compensation network at pin 2 (v comp ). the voltage at this pin rises linearly and so does the amplitude of the inpu t current. as soon as the output voltage v out reaches 80% of its rated level, the startup proc edure is finished and the normal voltage contro l takes over. in normal operation, the ic operates with a higher maximum current at ota1 and therefore with a higher volt age loop gain in order to improve the dynamic behavior of the device. the advantage of this technique is a so ft-start function with lower stress for the boost diode but without the risk of audible noise. 4. system protection the ic is equipped with various protection features to ens ure the pfc system in safe operating range. depending on the input line voltage (v in ) and output bus voltage (v out ), when these protections are active the conditions are shown in fig. 6 and 7. the following sections describe the func tionality of these protection features.
8565 preliminary linear integrated circuit unisonic technologies co., ltd 8 of 13 www.unisonic.com.tw qw-r114-004.b ? functional description(cont.) 4.1 brown-out protection (bop) input brown-out occurs if the input voltage v in falls below the minimum input voltage of the design (i.e. 85v for universal input voltage range) and the v cc has not entered into the v cc under voltage lockout level yet. for a system without bop, the boost converter will increasingly draw a higher current from the main s at a given output power which may exceed the maximum design values of the input current. the utc 8565 limits internally the current drawn from the mains and therefore also limits the input power. the difference of input and output power will result in decreasing output voltage. if the c ondition prolongs, the decreasing v out will terminate in output under voltage condition (ouv, 50% of rated), and the ic will be shut down (see section 4.5). fig. 8 shows the occurrence of bop in respect to the i sense voltage. the v in threshold for bop to occur is dependent on the voltage at i sense and thus the output power. the rated output power with a minimum v in (v in(min) ) is 2 r1 0.6 inmin out v = ) rated ( p due to the internal parameter tole rance, the maximum power with v in(min) before bop occurs is 2 1 r 73 . 0 inmin out v = (max) p and the bop takes over the normal operation under rated output power latest at an input voltage of 73 . 0 2 1 r out bopmax ) rated ( p = v 4.2 soft over current control (soc) the utc 8565 is designed not to support any output power that co rresponds to a voltage lo wer than -0.73v at the i sense pin. a further increase in the inducto r current, which results in a lower i sense voltage, will activate the soft over current control (soc). this is a soft c ontrol as it does not directly switch o ff the gate drive like the pcl. it acts on the nonlinear gain block to result in a reduced pwm duty cycle. 4.3 peak current limit (pcl) the utc 8565 is equipped with a cycle by cycle peak current protection feature. it is ac tive when the voltage at pin 5 (i sense ) reaches -1.08v. this voltage is am plified by op1 with a factor of -1.43 and connected to comparator c2 with a reference voltage of 1.5v as shown in fig. 9. a deglitcher with 300ns after the comparator improves noise immunity to the activati on of this protection.
8565 preliminary linear integrated circuit unisonic technologies co., ltd 9 of 13 www.unisonic.com.tw qw-r114-004.b ? functional description(cont.) 4.4 open loop protection / input under voltage protect (olp) whenever v sense voltage falls below 0.8v, or equivalently v out falls below 16% of its rated value, it indicates an open loop condition (i.e. v sense pin not connected) or an insufficient input voltage v in for normal operation. in this case, most of the blocks within the ic will be shutdown. the function is implemented using comparator c3 with a threshold of 0.8v as shown in the ic block diagram in fig. 2. 4.5 output under voltage detection (ouv) in the event of main interrupt or brow n-out condition, the pfc system is not abl e to deliver the rated output power. this will cause the output voltage v out to drop below its rated value. the ic provides an output under voltage detection that checks if v out is falling below 50% of its rated value. comparator c4 as shown in the device block diagram (fig. 2) senses the voltage at pin 1 (v sense ) with a reference of 2.5v. if comp arator c4 trips, the ic will be shut down as in olp. the ic will be r eady to restart if there is sufficient v in to pull v out out of olp. 4.6 over-voltage protection (ovp) whenever v out exceeds the rated value by 5%, the over-voltage pr otection ovp is active as shown in fig. 7. this is implemented by sensing the voltage at pin v sense with respect to a reference voltage of 5.25v. a v sense voltage higher than 5.25v will immediately r educe the output duty cycle, bypassing t he normal voltage loop control. this results in a lower input power to reduce the output voltage v out . 5. frequency setting the switching frequency of the pfc controller is fixed and c an be set by an external resistor r5 at freq pin. the pin voltage v freq is typically 2.5v. the corresponding capacitor for the oscillator is integrated in the device and the r5/frequency relationship is given at the ?electrical c haracteristic? section. the recommended operating frequency range is from 50khz to 250khz . as an example, a r5 of 33k ? at pin freq will set a switching frequency f sw of 133khz typically. 6. average current control 6.1 complete current loop fig. 10 show the complete system current loop. it consists of the current loop block wh ich averages the voltage at pin i sense , resulted from the inductor current flowing across r1. the averaged waveform is compared with an internal ramp in the ramp generator and pwm block. once the ramp crosses the average waveform, the comparator c1 turns on the driver stage through the pwm logic block. the nonlinear gain block defines the amplitude of the inductor current. the following sections describe the functionality of each individual blocks. l1 d1 c2 r4 r3 v out gate gate driver r s q pwm logic input from voltage loop nonlinear gain fault 4v s2 1.1ms +/-50 a (linear range) current loop compensation current loop ota2 + - utc 8565 r7 r1 r2 from full-wave retifier i sense i comp c3 c1 + - pwm comparator inductor current voltage proportional to averaged fig. 10 complete system current loop
8565 preliminary linear integrated circuit unisonic technologies co., ltd 10 of 13 www.unisonic.com.tw qw-r114-004.b ? functional description(cont.) 6.2 current loop compensation the compensation of the current loop is done at the icomp pin. this is the ota2 output and a capacitor c3 has to be installed at this node to ground (see fig. 10). under normal mode of operation, this pin gives a voltage which is proportional to the averaged inductor current. this pin is inte rnally shorted to 5v in the event of ic shuts down when olp and uvlo occur. 6.3 pulse width modulation (pwm) the ic employs an average current control scheme in c ontinuous conduction mode (ccm) to achieve the power factor correction. assuming the voltage loop is working and output voltage is kept constant, the off duty cycle d off for a ccm pfc system is given as out in v v off = d from the above equation, d off is proportional to v in . the objective of the current loop is to regulate the average inductor current such that it is proportional to the off duty cycle d off , and thus to the input voltage v in . fig. 11 shows the scheme to achieve the objective. the pwm is performed by the intersection of a ramp signal with the averaged inductor current at pin 3 (i comp ). the pwm cycle starts with the gate turn off for a duration of t off(min) (250ns typ.) and the ramp is kept discharged. the ramp is then allowed to rise after t off(min) expires. the off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. this resu lts in the proportional relationship between the average current and the off duty cycle d off . fig. 12 shows the timing diagrams of t off(min) and the pwm waveforms. 6.4 nonlinear gain block the nonlinear gain block controls the amplitude of the regulated inductor current. the input of this block is the voltage at pin v comp . this block has been designed to support the wide input voltage range (85-265v ac ).
8565 preliminary linear integrated circuit unisonic technologies co., ltd 11 of 13 www.unisonic.com.tw qw-r114-004.b ? functional description(cont.) 7. pwm logic the pwm logic block prioritizes the control input signals and generates the final logic signal to turn on the driver stage. the speed of the logic gates in this block, together with the width of the reset pulse t off(min) , are designed to meet a maximum duty cycle d max of 95% at the gate output under 133khz of operation. in case of high input currents which result in peak cu rrent limitation, the gate wi ll be turned off immediately and maintained in off state for the current pwm cycle. the signal t offmin resets (highest priority, overriding other input signals) both the current limit latch and the pwm on latch as illustrated in fig . 13. 8. voltage loop the voltage loop is the outer loop of the cascaded control scheme which controls the pfc output bus voltage v out . this loop is closed by the feedback sensing voltage at v sense which is a resistive divider tapping from v out . the pin v sense is the input of ota1 which has an internal reference of 5v. fig. 14 shows the import ant blocks of this voltage loop. 8.1 voltage loop compensation the compensation of the voltage loop is installed at the v comp pin (see fig. 14). this is the output of ota1 and the compensation must be connected at this pin to ground. the compensation is also responsible for the soft start function which controls an increasing ac input current during start-up. from full-wave retifier l1 r7 d1 r3 r4 c2 v out current loop + pwm generation v in av(i in ) nonlinear gain gate driver gate v sense v comp r6 c4 c5 ota1 5v - + utc 8565 fig. 14 voltage loop
8565 preliminary linear integrated circuit unisonic technologies co., ltd 12 of 13 www.unisonic.com.tw qw-r114-004.b ? functional description(cont.) 8.2 enhanced dynamic response due to the low frequency bandwidth of the voltage loop, the dynamic response is slow and in the range of about several 10ms. this may cause additional stress to the bus capacitor and the switching transistor of the pfc in the event of heavy load changes. the ic provides therefore a ?window detector? for the feedback voltage v vsense at pin 1 (v sense ). whenever v vsense exceeds the reference value (5v) by 5%, it will act on the nonlinear gain block which in turn affect the gate drive duty cycle directly. this change in duty cycle is bypassing the slow changing v comp voltage, thus results in a fast dynamic response of v out . 9. output gate driver the output gate driver is a fast totem pole gate drive. it has an in-built cross conduction currents protection and a zener diode z1 (see fig. 15) to protect the external transistor switch against undesirable over voltages. the maximum voltage at pin 7 (gate) is typically clamped at 11.5v. the output is active high and at v cc voltages below the under voltage lockout threshold v ccuvlo , the gate drive is internally pull low to maintain the off state. ? typical application circuit 85...265vac emi-filter switch auxiliary supply v cc pfc-controller protection unit voltage loop compensation pwm logic driver variable oscillator ramp generator nonlinear gain current loop compensation i sense gate freq i comp v out v sense v comp gnd utc 8565
8565 preliminary linear integrated circuit unisonic technologies co., ltd 13 of 13 www.unisonic.com.tw qw-r114-004.b utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.

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